The present invention relates to data processing and communication, and more specifically, to improved communication via a serial interface.
Serial interfaces are commonly employed in data processing systems to support communication between system components and input/output (I/O) or peripheral devices. Typically, data intended for transmission via the serial interface is received in units (frames) of one or more bytes, and these bytes are serialized into a stream of bits that is transmitted over the serial channel in bit order and byte order from a transmitting component to a receiving component. For example, if a frame containing four bytes is to be transmitted, bit 0 to bit 7 of the first byte is transmitted, followed by bit 0 to bit 7 of the second byte, followed by bit 0 to bit 7 of the third byte, and finally bit 0 to bit 7 of the fourth byte. The receiving component may then deserialize the serial stream of bits to reassemble the original frame.
In conventional serial interfaces, it is common at the data link layer for frames to be variable in length. As a consequence, the receiving component must fully receive and correctly decode a first frame in order for the receiving component to be able to correctly identify the beginning of a subsequent second frame and to correctly decode it. This restriction increases the complexity and processing latency of the receiving component, which may already have a significantly lower operating frequency than the transmitting component.